Date: Thu, 07 Nov 1996 19:17:46 GMT
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Last-modified: Tue, 08 Oct 1996 19:17:57 GMT
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<TITLE>Eric's Home Page</TITLE>
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<!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><IMG SRC="http://www.cs.wisc.edu/~ericro/caray.gif" ALT="-burp-" ALIGN=MIDDLE> <br>
"Passsth me another cold Budweisther !!"
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<dl>
<dt> <b>Address</b>
<dd>  <!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><a href="http://www.cs.wisc.edu/">
Computer Sciences Department</a> <br>
<!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><a href="http://www.wisc.edu">
University of Wisconsin - Madison</a> <br>
1210 West Dayton Street <br>
Madison, WI 53706 <br>
<br>
<!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><a href="http://www.engr.wisc.edu/">
Department of Electrical and Computer Engineering</a> <br>
University of Wisconsin - Madison</a> <br>
1415 Johnson Drive <br>
Madison, WI 53706 <br>
<dt> <b>Office</b>
<dd>  3652 ECE
<dt> <b>Phone</b>
<dd>  (608) 265-3826
<dt> <b>E-mail</b>
<dd>  <!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><a href="http://www.cs.wisc.edu/cgi-bin/finger?ericro">
ericro@cs.wisc.edu</a>
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<P>
<dl>
<dt> <b>Research Area</b>
<dd> Computer Architecture <br>
<dt> <b>Advisor</b>
<dd> Professor J.E. Smith
<DT><B>Research Topics</B>
<DD>
<UL>
<LI> <!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><A HREF ="http://www.cs.wisc.edu/~mscalar">Kestrel (Multiscalar) Project</A>
<LI> Instruction-Level Parallelism (ILP)
<LI> High Bandwidth Instruction Fetch Mechanisms
<LI> Branch Prediction Confidence, Branch Mispredict Tolerance
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<b>Publications:</b>
<blockquote>
<!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><A HREF = "http://www.cs.wisc.edu/~ericro/TC_micro29.ps">
"Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching"</A>,
  Eric Rotenberg, Steve Bennett, and James E. Smith,
  To appear in <i>Proceedings of the 29th Annual International Symposium on
  Microarchitecture</i>, December 1996.
</blockquote>
<blockquote>
<!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><A HREF = "http://www.cs.wisc.edu/~ericro/CONF_micro29.ps">
  "Assigning Confidence to Conditional Branch Predictions"</A>,
  Erik Jacobsen, Eric Rotenberg, and James E. Smith,
  To appear in <i>Proceedings of the 29th Annual International Symposium on
  Microarchitecture</i>, December 1996.
</blockquote>
<blockquote>
<!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><A HREF = "http://www.cs.wisc.edu/Dienst/UI/2.0/Describe/ncstrl.uwmadison%2fCS-TR-96-1310">
  "Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching"</A>,
  Eric Rotenberg, Steve Bennett, and James E. Smith,
  University of Wisconsin - Madison Technical Report #1310, April 1996.<br>
</blockquote>
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<P> <!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><A HREF ="http://www.cs.wisc.edu/~ericro/resume.ps">Resume</A>
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